IBM Unpacks World's 1st Sub-1 Nanometer Chip Technology
In what is billed as a major semiconductor breakthrough, Tech giant IBM introduced the world's first sub-1 nanometer (nm) chip technology, featuring a revolutionary transistor architecture at the 0.7 nm, or 7 angstrom node
In what is billed as a major semiconductor breakthrough, Tech giant IBM introduced the world's first sub-1 nanometer (nm) chip technology, featuring a revolutionary transistor architecture at the 0.7 nm, or 7 angstrom node.
Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.
"The achievement marks a landmark moment for an industry facing the physical limits of traditional chip scaling", IBM said.
Sub-1 nm vs 2 nm chip
IBM's new sub-1 nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM's 2 nm chip, unveiled in 2021.
Enabled by a series of structural and material innovations, including IBM's groundbreaking three-dimensional nanostack architecture, the technology demonstrates how continued gains in performance and efficiency remain possible even as chip features approach atomic dimensions.
The new chip is projected to offer a substantial improvement in capability — up to 50 percent more performance, or 70 percent greater energy efficiency than IBM's 2 nm node chips, supercharging compute for applications ranging from generative AI and cloud infrastructure to next-generation electronic devices.
Nanostack Architecture
IBM said it's researchers developed an entirely new transistor architecture, called "nanostack", to produce this chip. This is the industry's first known three-dimensional, nanosheet-based design.
"Nanostack represents a major advance beyond nanosheet technology, the industry's current leading-edge architecture, invented by IBM", the tech giant said.
The nanostack design vertically stacks and staggers transistors, taking advantage of 3D sequential integration to pack more transistors onto a chip. The design also unlocks the use of different material combinations within each stacked layer, optimizing performance and power efficiency of each transistor independent of the other.
IBM's nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance.
"Together, these results confirm the nanostack technology can be physically built and supports real computation", IBM said.
Furthermore, IBM researchers at VLSI 2026 demonstrated that the nanostack architecture provides 40 percent scaling in SRAM, unlocking the ability of chip designers to create much more efficient chips while also supporting the high-bandwidth data demands of advanced AI workloads.
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